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A second file is used to assign values to the components and is instantiated inside the cell.
This data cell file is
‘/Simulate/Napados/Net/SWC_Integrator/Test/Integrator_NI.dat’
The last file is the netlist of the simulation.
The simulation file is
‘/Simulate/Napados/Net/SWC_Integrator/Test/Integrator_NI.nap’
The file contains the instantiation of a non-overlapped clock generator, the cell describing
the integrator, a ‘pwl’ cell describing the input, and the location of the data file containing
the parameters. A change in clocks percutes the value of the switches resistances.
The instantiated pwl cell is
‘/Simulate/Napados/Net/Clock/clock12.net’